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lucask07
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covg_fpga
FPGA and Python experiment code for the digital ion channel amplifier project.
GNU General Public License v3.0
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Ephys meas
#43
lucask07
opened
3 months ago
0
update SPI DRIVE to 8 and test
#42
lucask07
closed
1 year ago
0
Ddr adc pause
#41
lucask07
closed
1 year ago
0
adding modifications to bath clamp vstep
#40
lucask07
closed
1 year ago
0
Experiment datastreams
#39
lucask07
closed
1 year ago
0
Observer
#38
lucask07
closed
1 year ago
0
All tests
#37
lucask07
closed
1 year ago
0
Remove DDR params
#36
Ajstros
closed
1 year ago
0
Datastream
#35
lucask07
closed
1 year ago
2
calibration updates into observer branch
#34
lucask07
closed
1 year ago
0
extra comment in electrodes.py
#33
lucask07
closed
1 year ago
0
Correct conflicts in ep_defines file to fix failing pyripherals tests
#32
Ajstros
closed
1 year ago
1
Longer dac ddr
#31
lucask07
closed
2 years ago
0
Bitfile versioning
#30
Ajstros
closed
2 years ago
0
Add Vm graph and inject current
#29
Ajstros
closed
2 years ago
0
ADS8686 channel 'A', 'B' not synchronized
#28
lucask07
closed
1 year ago
1
Plotting of DDR data streams is too memory intensive
#27
lucask07
closed
2 years ago
3
Ads conv cnt fpga
#26
lucask07
closed
2 years ago
1
Standardize Xilinx synthesis and elaboration options
#25
lucask07
opened
2 years ago
0
Determine FPGA bit-file version
#24
lucask07
opened
2 years ago
0
ADS8686 sequencer position is unknown in DDR readings
#23
lucask07
closed
2 years ago
1
DAQ board set_dac_gain
#22
lucask07
opened
2 years ago
0
Generalize clamp step response DDR functions
#21
Ajstros
closed
2 years ago
2
Remove pyripherals files
#20
Ajstros
closed
2 years ago
2
modified endpoints and advance_endpoints so that REGBRIDGE_OFFSET end…
#19
lucask07
closed
2 years ago
5
modified endpoints and advance_endpoints so that REGBRIDGE_OFFSET end…
#18
lucask07
closed
2 years ago
1
os.add_dll_directory does not work as expected on Windows with anaconda
#17
lucask07
closed
2 years ago
1
Add MAC frontpanel setup to interfaces.py
#16
lucask07
closed
2 years ago
1
MAC installation instructions
#15
lucask07
closed
2 years ago
1
DAC80508_ADS8686_test.py executes open_rigol_supply fails during pytest collection
#14
lucask07
closed
2 years ago
3
Opal Kelly files should be removed from the repository
#13
lucask07
closed
2 years ago
1
Reorganize for packaging
#12
Ajstros
closed
2 years ago
2
Update packaging branch from daq_v2
#11
Ajstros
closed
2 years ago
0
Update max5802_i2c.py
#10
NathanLoPresto
closed
3 years ago
0
Update max5802_i2c.py
#9
NathanLoPresto
closed
3 years ago
0
LVDS needs to be on clock pin?
#8
lucask07
closed
2 years ago
0
Wb_SignalConverter: state register sensitivity list
#7
lucask07
closed
2 years ago
0
Wb_SignalConverter: avoid reg initializations
#6
lucask07
closed
2 years ago
1
WbSignal_converter: create 1 clock cycle pulse
#5
lucask07
closed
2 years ago
0
Still alive and state using LEDs
#4
lucask07
closed
2 years ago
0
Module for setting and reading generic I/O levels
#3
lucask07
closed
2 years ago
0
Fast DAC signal playback
#2
lucask07
closed
2 years ago
0
Implement Opal Kelly registers
#1
lucask07
closed
2 years ago
0