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rlindsberg
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1331IL-VHDL-Design
Microprocessor AR 4003
GNU General Public License v3.0
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Laboration 5 done, sim passed
#53
rlindsberg
closed
6 years ago
0
BRA 13 fatal error
#52
gitgnmn
closed
6 years ago
3
Timing issue for SUB
#51
rlindsberg
opened
6 years ago
3
Code rom output never runs
#50
rlindsberg
opened
6 years ago
4
Test bench for AR4003 (processor.vhd) doesn't work
#49
rlindsberg
opened
6 years ago
1
Warning (21074): Design contains 2 input pin(s) that do not drive logic
#48
rlindsberg
opened
6 years ago
1
Registerfile patch
#47
rlindsberg
closed
6 years ago
0
Register file doesn't work
#46
rlindsberg
closed
6 years ago
2
Fix huge bug that array size doesn't match
#45
rlindsberg
closed
6 years ago
0
Flabb4 gitnmn backup
#44
rlindsberg
closed
6 years ago
2
Lab 4 Controller design completed, with simple test bench
#43
gitgnmn
closed
6 years ago
54
Fix state toggles like crazy..
#42
rlindsberg
closed
6 years ago
0
program_count => program_count + 1; is in the wrong place.
#41
gitgnmn
closed
6 years ago
1
CASE isn't working as it should (in my opinion)
#40
gitgnmn
closed
6 years ago
2
Output pins are stuck at VCC or GND
#39
rlindsberg
opened
6 years ago
2
Lab 3 complete, simulation passed
#38
rlindsberg
closed
6 years ago
13
New RAM design
#37
rlindsberg
closed
6 years ago
0
New RAM design
#36
rlindsberg
closed
6 years ago
0
Write and read sim passed
#35
rlindsberg
closed
6 years ago
0
Cannot read from RAM
#34
rlindsberg
closed
6 years ago
0
A1.2 1.3 sim passed
#33
rlindsberg
closed
6 years ago
0
Writing tests passed, reading test still fails
#32
rlindsberg
closed
6 years ago
0
Compare L3 code
#31
rlindsberg
closed
6 years ago
0
Counter test bench fails
#30
rlindsberg
closed
6 years ago
0
Should not change value of a signal on clock edge and asynchronously
#29
rlindsberg
closed
6 years ago
0
Super final labb 2 code
#28
gitgnmn
closed
6 years ago
2
Preparations for lab 2 done, Simulation 50% passed
#27
rlindsberg
closed
6 years ago
7
Simulation fails
#26
rlindsberg
closed
6 years ago
2
Compile error patches
#25
rlindsberg
closed
6 years ago
1
Attribute "active" is not supported
#24
rlindsberg
closed
6 years ago
0
If not allowed to use outside process
#23
rlindsberg
closed
6 years ago
0
No implementation of CLK
#22
rlindsberg
closed
6 years ago
0
Near text "when"; expecting ";"
#21
rlindsberg
closed
6 years ago
0
Cannot call subprogram "add_overflow"
#20
rlindsberg
closed
6 years ago
0
Outsignal y is undefined
#19
rlindsberg
closed
6 years ago
1
ALU flags need to be reset at Begin
#18
rlindsberg
closed
6 years ago
0
Variable is not constrained..
#17
rlindsberg
closed
6 years ago
0
Missing "... when Others" in closure
#16
rlindsberg
closed
6 years ago
0
Overflow flag NOT WORKING
#15
rlindsberg
closed
6 years ago
0
Wrong bit number
#14
rlindsberg
closed
6 years ago
3
Last of labb1 (2.3 & 2.4)
#13
gitgnmn
closed
6 years ago
1
Assignment 2.3
#12
rlindsberg
closed
6 years ago
2
added 'KLAR' to 1.4 and filled in results in table
#11
gitgnmn
closed
6 years ago
1
fixed result table in delay.md
#10
gitgnmn
closed
6 years ago
1
Preparations done for lab 1
#9
rlindsberg
closed
6 years ago
2
Adder 8 not correct simulating result..
#8
rlindsberg
closed
6 years ago
0
Cleaning
#7
gitgnmn
closed
6 years ago
1
Functional 4 Bit CLA simulation passed
#6
rlindsberg
closed
6 years ago
2
Compile failed in Quartus; Error loading design in ModelSim
#5
rlindsberg
closed
6 years ago
17
4 Bit Ripple Adder sim passed
#4
rlindsberg
closed
6 years ago
2
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