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This reproduces in 3.480 and I don't see any related code changes in the 3.483 version. Continuous assignments in an interface cause a missing method error for new_contassign which exists on Verilog::…
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### Description
I find myself doing this manual navigation a lot:
![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/708c1923-8f36-4d28-a6ef-55e2291e4b35)
Ideally I cou…
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### Before start
- [X] I have read the [XiangShan Documents](https://xiangshan-doc.readthedocs.io/zh_CN/latest). 我已经阅读过香山文档。
- [X] I have searched the previous issues and did not find anything releva…
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TerosHDL:Global output: 2024-06-19 09:53:02.780 [info] [00000.001204] ERROR: Can't guess frontend for input file `d:/workSpace/sim/fifo/axis_async_fifo.v;' (missing -f option)!
When I'm in the CMD wi…
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It seems that the extension parses the include globs and expects the paths provided in the include globs to be inside the workspace always. This is not necessarily the case in projects where we refer …
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**Describe the bug**
When trying to generate Verilog for a fairly complex module written in DSLX the compiler segfaults.
**To Reproduce**
Steps to reproduce the behavior:
- Follow the XL…
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The std::iterator class will be deprecated in C++17:
- https://stackoverflow.com/questions/43268146/why-is-stditerator-deprecated
In CI, the GCC 12 and CLANG 14 build show the deprecation warnings…
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I attempted to convert this project to Verilog so I could use it in Xilinx ISE.
I used a utility called sv2v (https://github.com/zachjs/sv2v).
I had to change 3 wires to reg after conversion and the…
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You may choose not to do this, depending on how many people want it,thanks !
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Hello!
I got this error for code:
error: Number of outputs does not match the number of children!
error: called from
get_child_names at line 276 column 17
visitBranch at line 184 column …