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### Version
yosys 0.41+126
### On which OS did this happen?
Linux
### Reproduction Steps
Hello,
I encountered an error while using Yosys to read a Verilog file. The steps and the error message a…
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## 端口连接规则
### 输入端口
模块例化时,从模块外部来讲, input 端口可以连接 wire 或 reg 型变量。这与模块声明是不同的,从模块内部来讲,input 端口必须是 wire 型变量。
### 输出端口
模块例化时,从模块外部来讲,output 端口必须连接 wire 型变量。这与模块声明是不同的,从模块内部来讲,output 端口可以是 wire 或 re…
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This is a proposal for discussion.
The idea is to switch the linter from Verilator to Veriable.
https://github.com/chipsalliance/verible
Rationale
In addition to a command line lint, Verible…
zapta updated
3 months ago
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[nn_verilog_a_l0_2_l1_2_l2_2.va.txt](https://github.com/pascalkuthe/OpenVAF/files/14942978/nn_verilog_a_l0_2_l1_2_l2_2.va.txt)
[openvaf-crash-1712820826.log](https://github.com/pascalkuthe/OpenVAF/…
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When implementing a simple UART test, sending 2 RTL hard-coded bytes every 1.6 ms on tx, strange results were observed: **Some combinations of bytes transmit correctly, some don't**. Important notes: …
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https://www.bilibili.com/video/BV12y4y1v7V3?vd_source=9fe1c020c4b9fcfff5f8417a69f07f6c
https://hdlbits.01xz.net/wiki/Main_Page
https://www.edaplayground.com/playgrounds
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I'm working on a React application that utilizes the react-monaco-editor component for Verilog language editing. I'm currently investigating language server options for Verilog support within the edit…
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Hi,
I discovered a problem on our AXIDownConverter.
When AXI Master initiate subword access, our AXIDownConverter would generate illegal request to downstream.
See following examples:
For a …
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Hi~
SpinalHDL language itself has good generalization and maintainability,
But the quality of the verilog code it generates is not high, the maintainability is poor, and it is difficult to meet the…
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### Version
Yosys 0.42+12 (git sha1 62bff3a20, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os)
### On which OS did this happen?
Linux
### Reproduction Steps
try to synthesize the output of litex
…