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Implement LETC Core AXI FSM
#61
JZJisawesome
opened
8 months ago
0
Implement LETC Core Stage D
#60
JZJisawesome
opened
8 months ago
0
Implement LETC Core Stage W
#59
JZJisawesome
opened
8 months ago
0
Implement LETC Core Stage E1
#58
JZJisawesome
opened
8 months ago
0
Better filelists
#57
JZJisawesome
opened
8 months ago
0
Yosys for Synthesis And Formal Verif
#56
JZJisawesome
opened
8 months ago
1
UVM
#55
JZJisawesome
opened
8 months ago
0
Set up Conductor repo
#54
nickchan2
opened
8 months ago
0
Add page about LETC boot flow to wiki
#53
JZJisawesome
closed
8 months ago
1
Git + Vitis
#52
nickchan2
closed
8 months ago
2
C++ RVSW Weirdness
#51
JZJisawesome
opened
8 months ago
1
Emulation of instructions for LETC not supported in hardware
#50
JZJisawesome
opened
8 months ago
1
Implement more UART registers
#49
JZJisawesome
closed
8 months ago
1
UART virtual serial console
#48
JZJisawesome
closed
8 months ago
1
Figure out hardware platform in Vivado to make Conductor's life easier
#47
JZJisawesome
opened
8 months ago
0
UART Race Condition
#46
JZJisawesome
closed
8 months ago
1
Move the loader functions to AGI utils
#45
nickchan2
opened
9 months ago
0
Get RVSW to compile on MacOS
#44
nickchan2
opened
9 months ago
3
Debug smode interrupts
#43
JZJisawesome
closed
8 months ago
3
Master Repo
#42
nickchan2
opened
9 months ago
0
Actually disable assertions in release mode. Whoops!
#41
JZJisawesome
opened
9 months ago
1
Find a better way to keep the wiki homepage and org readme in sync
#40
JZJisawesome
closed
9 months ago
3
Fix broken U-mode programs
#39
JZJisawesome
closed
9 months ago
7
Improve project appearance to newcomers
#38
JZJisawesome
opened
9 months ago
2
Better linux/initrd
#37
JZJisawesome
closed
8 months ago
2
EEI
#36
JZJisawesome
opened
9 months ago
0
Why does the m-mode linux kernel die if ubsan is enabled in the config?
#35
JZJisawesome
opened
9 months ago
0
Create a tentative list of commands we want for Conductor
#34
nickchan2
opened
9 months ago
1
Cleanup LETC
#33
JZJisawesome
closed
9 months ago
2
Virtual serial port
#32
nickchan2
opened
10 months ago
2
Clean up logging interface
#31
nickchan2
closed
9 months ago
1
Move LETC onenote notebook to a personal account from UW
#30
JZJisawesome
opened
10 months ago
2
Align CSR implementation in IRVE with EEI
#29
nickchan2
opened
10 months ago
3
Create Wiki Page: Setting up LETC in Vivado & Vitis
#28
nickchan2
opened
10 months ago
1
Improve Word methods
#27
nickchan2
closed
9 months ago
4
Memory refactoring
#26
nickchan2
opened
10 months ago
0
Fix or remove Makefile
#25
nickchan2
closed
9 months ago
2
LETC: Reset, Clocking, and Boot
#24
JZJisawesome
opened
10 months ago
1
LETC: Core Design
#23
JZJisawesome
opened
10 months ago
0
LETC: Matrix Design
#22
JZJisawesome
opened
10 months ago
0
Design conductor project
#21
JZJisawesome
opened
10 months ago
1
Improve readmes AGI-wide
#20
JZJisawesome
opened
10 months ago
1
Braindump everything into issues
#19
JZJisawesome
closed
9 months ago
2
LETC: Bus protocol selection
#18
JZJisawesome
closed
8 months ago
2
Make it more clear in other AGI projects' readmes why issues are disabled
#17
JZJisawesome
closed
9 months ago
3
Code cleanup in IRVE
#16
nickchan2
closed
9 months ago
3
Fix Broken Paging With S-Mode kernel
#15
nickchan2
closed
9 months ago
6
Document custom instructions in IRVE
#14
nickchan2
opened
10 months ago
1
Interrupts/clint/plic/etc in IRVE
#12
JZJisawesome
opened
10 months ago
0
Fix LTO issues when it is enabled in RVSW (it worked fine last summer)
#11
JZJisawesome
closed
9 months ago
1
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