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TheSystemDevelopmentKit
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rtl
Package for rtl (i.e. Verilog and VHDL ) simulation control
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Cosimulation of Verilog top + VHDL external files
#48
Roenski
closed
1 year ago
1
V1.9 rc
#47
mkosunen
closed
1 year ago
0
Cosimulation of Verilog DUT with VHDL external files
#46
Roenski
closed
1 year ago
1
Icarus
#45
Anttitarkka
closed
2 years ago
0
Refactor
#44
mkosunen
closed
1 year ago
4
Copy symlinks instead of link targets
#43
chiplet
closed
2 years ago
0
Modify rtl testbench for A-Core post route simulation
#42
chiplet
closed
1 year ago
0
Path for additional vlogmodulefiles generated incorrectly for Icarus simulations
#41
Roenski
closed
2 years ago
1
Improve verilog module IO parsing
#40
chiplet
closed
2 years ago
1
verilog_module doesn't know how to parse IOs post-route verilog netlist
#39
chiplet
opened
2 years ago
0
Add new functionalities for RTL simulation modifyability
#38
Roenski
closed
2 years ago
1
Icarus
#37
Anttitarkka
closed
2 years ago
3
Inverter testbench reads input and writes output at the same time
#36
Anttitarkka
closed
2 years ago
2
Add support for custom connectors
#35
Roenski
closed
2 years ago
1
Improvements for Verilog testbench indentation
#34
Roenski
closed
2 years ago
1
Add parameter word to testbench parameter list
#33
Roenski
closed
2 years ago
1
Add `parameter` in front of each parameter in testbench parameter list
#32
Roenski
closed
2 years ago
1
Add vlogcompargs to pass arguments during verilog compilation
#31
chiplet
closed
2 years ago
0
Use GTKWave for interactive mode
#30
Roenski
closed
2 years ago
1
Add support for Icarus Verilog
#29
Roenski
closed
2 years ago
2
Verilator support
#28
mkosunen
closed
1 year ago
1
Add suport for mixed mode compilation for Questa
#27
mkosunen
closed
2 years ago
1
Typo in setter
#26
chiplet
closed
1 year ago
1
Module fix
#25
mkosunen
closed
2 years ago
0
added vlibsmap
#24
mkosunen
closed
2 years ago
0
Vhdl sources patch
#23
mkosunen
closed
2 years ago
1
Check for existing sources before copying
#22
chiplet
closed
2 years ago
2
Clarified simulation file cleanup process
#21
mkosunen
closed
2 years ago
1
Copy simulations sources to `simulations/` when running RTL simulations
#20
chiplet
closed
2 years ago
9
Add rtl_timeunit property
#19
mkosunen
closed
2 years ago
1
Cannot call set_control_data(init=0) twice
#18
chiplet
opened
3 years ago
0
V1.7 RC
#17
mkosunen
closed
2 years ago
0
Simulation directory not cleaned up properly
#16
ojarvin
closed
2 years ago
1
Refactoring simulations directory
#15
ojarvin
closed
3 years ago
10
Entity state saving to binary file
#14
ojarvin
closed
3 years ago
0
Use verilog time type for event timestamps
#13
chiplet
closed
3 years ago
1
Optimize set_control_data
#12
mkosunen
closed
3 years ago
4
Revert "Optimize event based IO file creation"
#11
mkosunen
closed
3 years ago
0
V1.6 rc
#10
mkosunen
closed
3 years ago
0
Optimize event based IO file creation
#9
chiplet
closed
3 years ago
0
Fix right limits
#8
Kovalevy
closed
3 years ago
0
WIP: `verilog_connector` fix
#7
chiplet
closed
3 years ago
1
Add valid input checks to verilog_module
#6
chiplet
opened
3 years ago
0
Cleanup of sram-dev
#5
mkosunen
closed
3 years ago
1
Release v1.5
#3
mkosunen
closed
3 years ago
0
rtlsim directory not created
#2
mkosunen
closed
3 years ago
1
Add support for Verilator
#4
mkosunen
closed
1 month ago
4
V1.3 rc
#1
mkosunen
closed
4 years ago
0
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