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jameshegarty
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rigel
Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FPGAs, and also can compile to fast x86 test code using Terra.
MIT License
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Framed
#125
jameshegarty
closed
6 years ago
2
Regout
#124
jameshegarty
closed
6 years ago
1
Python
#123
jameshegarty
closed
6 years ago
0
Sparsewrite
#122
jameshegarty
closed
6 years ago
1
Nonalignedrw
#121
jameshegarty
closed
6 years ago
1
Non128
#120
jameshegarty
closed
6 years ago
1
Regsimpl
#119
jameshegarty
closed
6 years ago
1
More bram options
#118
jameshegarty
closed
6 years ago
1
Improvepipelining
#117
jameshegarty
closed
6 years ago
1
Cyclecheck
#116
jameshegarty
closed
6 years ago
1
Donebit
#115
jameshegarty
closed
6 years ago
1
Generators
#114
jameshegarty
closed
6 years ago
0
initial
#113
jameshegarty
closed
6 years ago
0
Soc travis
#112
jameshegarty
closed
6 years ago
2
initial
#111
jameshegarty
closed
6 years ago
1
wrapper verilog fixes
#110
jameshegarty
closed
6 years ago
0
change systolic onlyWire setting into a :pipelineModule() function?
#109
jameshegarty
opened
6 years ago
0
Soc
#108
jameshegarty
closed
6 years ago
1
Remove stall domains
#107
jameshegarty
opened
6 years ago
0
Why doesn't everything get a reset fn?
#106
jameshegarty
opened
6 years ago
2
Wrapperfix
#105
jameshegarty
closed
6 years ago
0
Runtimegpio
#104
jameshegarty
closed
6 years ago
1
fix to problem with memoize
#103
jameshegarty
closed
6 years ago
0
initial
#102
jameshegarty
closed
6 years ago
0
Codesizeopt
#101
jameshegarty
closed
6 years ago
0
Vfix
#100
jameshegarty
closed
6 years ago
0
Platform mk
#99
jameshegarty
closed
6 years ago
4
Zu9 board support
#98
jameshegarty
closed
6 years ago
1
fix clocking issue with BUFG_PS
#97
muzafferkal
closed
6 years ago
0
Mkal zu9 fix
#96
muzafferkal
closed
6 years ago
2
update compile script to include all necessary files generated by ver…
#95
hofstee
closed
6 years ago
2
Scriptcleanup
#94
jameshegarty
closed
6 years ago
2
Harnessrefactor
#93
jameshegarty
closed
6 years ago
2
Luacov
#92
jameshegarty
closed
6 years ago
0
Globals
#91
jameshegarty
closed
6 years ago
0
Taps perf regression
#90
jameshegarty
opened
6 years ago
0
-Wno-UNOPTFLAT
#89
jameshegarty
opened
6 years ago
0
Removenulls
#88
jameshegarty
closed
6 years ago
0
remove nil->Handshake(A)
#87
jameshegarty
opened
6 years ago
1
terra :calculateHandshake() not created if input/output type aren't handshake
#86
jameshegarty
opened
6 years ago
1
Staging
#85
hofstee
closed
6 years ago
0
Code Coverage
#84
jameshegarty
opened
6 years ago
0
Zynq10
#83
jameshegarty
closed
7 years ago
0
Remove multiple verilog build targets generated by lua
#82
jameshegarty
closed
6 years ago
1
Remove multi-function support from systolic?
#81
jameshegarty
opened
7 years ago
0
systolic: Onlywire should be a property of :toVerilog()?
#80
jameshegarty
opened
7 years ago
1
Mid Level IR
#79
jameshegarty
opened
7 years ago
0
constant value out of range
#78
hofstee
opened
7 years ago
0
Rv->rv case not handled
#77
jameshegarty
opened
7 years ago
0
Nameconflicts
#76
jameshegarty
closed
7 years ago
0
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