riscv riscv-aia issues - Githubissues

riscv / riscv-aia

https://jira.riscv.org/browse/RVG-59

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A question of Interrupt filtering？

#105 ZeyueShen opened 4 days ago
0
Question about the condition of response for interrupt injected by hvictl

#104 myx922 closed 4 days ago
6
When vsiselect is in the range of 0x070–0x0FF, does access to vsireg2 belong to IMSIC states?

#103 Jahhow opened 2 weeks ago
0
Supervisor-level iprio configurability

#102 evgeniy-paltsev opened 3 weeks ago
2
mvien/mip behavior

#101 jiahzhang closed 1 week ago
1
Limitation access to the APLIC machine-level interrupt domain without PMP entries

#100 nonufrienko closed 4 days ago
2
Is hstatus.VGEIN used to index guest interupt files when accessing iCSR via VSISELECT/VSIREG window?

#99 zengderui closed 6 days ago
2
Can hvictl inject an interrupt with IID=0 and IPRIO=0?

#98 zhuotianshu opened 1 month ago
1
If S external interrupt is injected to S with mvien & mvip than there is no clear rule to determine its priority

#97 evgeniy-paltsev opened 1 month ago
2
Question of a machine-level trap handler described in aia spec(5.2.2)

#96 ZeyueShen opened 2 months ago
2
mtopi/stopi values when mnstatus.NMIE=0

#95 nonufrienko closed 2 months ago
2
Can AIA only support 2047 EIID maximum?

#94 zhangdujiao closed 1 week ago
3
AIA: contradiction in bits 12:0 of hvip description

#93 evgeniy-paltsev closed 1 month ago
2
Can different interrupt sources be directed to different die in one APLIC?

#92 zhangdujiao closed 2 months ago
1
What's the value of stopi.IPRIO when using mvien and mvip to generate a SEI that traps to S mode?

#91 zhuotianshu opened 3 months ago
5
Should virtual supervisor domain be implemented in APLIC while hypervisor (virtual supervisor) is supported?

#90 Steven-Li-Xiaogang closed 3 months ago
1
How to distinguish IPI and external interrupt if using IMSIC to accomplish IPI

#89 zhangdujiao closed 2 months ago
2
Fix minor typo

#88 pdonahue-ventana closed 1 week ago
1
Fixing typo

#87 xieby1 closed 1 week ago
1
Does mstateen0[58]=0 take precedence over hstatus.VGEIN=0?

#86 Jahhow opened 4 months ago
1
How to define NMI in AIA architecture?

#85 zhangdujiao closed 3 months ago
1
Clarify "Access control by the state-enable CSRs"

#84 wissygh closed 5 months ago
2
ASCII doc broken text

#83 albert-azcarate closed 5 months ago
3
Is there any requirement about the speed of arbitration or the interrupt infomation transfer?

#82 zhuotianshu closed 5 months ago
5
Update Makefile to support docker build

#81 somyadashora closed 5 months ago
1
Optional setting of interrupt pending when writing sourcecfg?

#80 kdockser closed 5 months ago
1
MVIP.STIP

#79 jiahzhang closed 6 months ago
2
Conflict register model between MVIEN and HVIEN

#78 zetalog opened 7 months ago
1
mvien[1]

#77 Mei-x-l opened 7 months ago
1
local interrupts in sip and vsip may be cleared when other CSRs change

#76 jhauser-us opened 8 months ago
0
About the possibility of IOMMU examining ie bit before sending notify MSI.

#75 zhuotianshu opened 8 months ago
0
Why the priority of the third candidate of vstopi is 256?

#74 zhuotianshu closed 8 months ago
7
Does SEI in VS mode use default priority?

#73 zhuotianshu opened 8 months ago
2
Can interrupt identity >63 cause a trap in non virtualized mode?

#72 zhuotianshu closed 8 months ago
2
Are priorities of virtual interrupts configurable to HS-mode through iprio array?

#71 YenHaoChen opened 8 months ago
3
About the "sticky" property of sip.

#70 zhuotianshu opened 8 months ago
1
workflow updates

#69 kersten1 closed 1 week ago
1
How to distinguish APLIC interrupt in MSI mode?

#68 X547 closed 8 months ago
4
What's the purpose of virtual interrupts?

#67 zhuotianshu opened 9 months ago
3
Behavior of accessing vsireg at vsiselect addresses 0x30~0x3f from HS-mode.

#66 YenHaoChen closed 8 months ago
2
Add a comment calling out the software-writable bit behind mip.SEIP

#65 jhauser-us opened 9 months ago
0
Conflicting sentences about mvip[9] and mip[9] when mvien[9]=0

#64 YenHaoChen closed 9 months ago
4
Possible typos in table 6.1

#63 jrahmeh closed 9 months ago
2
Question regarding mvip[9]

#62 gzaitd opened 9 months ago
2
How hvictl affect vstopi? Is every value legal?

#61 n1240549 opened 10 months ago
1
Does interrupts have priority when aplic forward through MSI? How to send MSI if 1023 interrupts arrive simultaneously

#60 vang2333 closed 8 months ago
1
vstopi behavior

#59 umcann123 closed 12 months ago
4
APLIC Level sensitive interrupts in MSI mode

#58 gzaitd closed 12 months ago
2
APLIC's domaincfg.IE bit and idelivery registers affect only interrupt delivery

#57 jhauser-us opened 1 year ago
0
IMSIC interrupt file eidelivery register affects only external interrupt in *ip CSR

#56 jhauser-us opened 1 year ago
0