stiggy87 source_to_inst issues

stiggy87 / source_to_inst

This is a TCL script that will take in Verilog and VHDL files and generate an instantiation template appropriately for the user to use in their design.

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issues

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If user instantiates a primitive, script breaks

#16 stiggy87 opened 11 years ago
0
Verilog module name is not correct

#15 stiggy87 closed 11 years ago
0
Verilog macro expansion

#14 stiggy87 opened 11 years ago
1
input/output/inout (Verilog) in signal names causes issues

#13 stiggy87 opened 11 years ago
1
Verilog: Port list is on per-line, not same line

#12 stiggy87 closed 11 years ago
1
Verilog: If open ( is not on the same line as module, fails

#11 stiggy87 closed 11 years ago
0
What is the runtime for a large file or large list?

#10 stiggy87 opened 11 years ago
0
Remove -filetype switch

#9 stiggy87 closed 11 years ago
1
Deletion of file (Windows-only)

#8 stiggy87 closed 11 years ago
2
Support if there are multiple entities/modules in a file

#7 stiggy87 closed 11 years ago
5
Clean up template statements

#6 stiggy87 closed 11 years ago
1
Add switches to the procedure

#5 stiggy87 closed 11 years ago
1
Repo needs test files

#4 stiggy87 closed 11 years ago
2
Missing capabilities with styles of Verilog/VHDL

#3 stiggy87 closed 11 years ago
2
Missing Usage capabilities

#2 stiggy87 closed 11 years ago
1
Script claims bad brace, but code doesn't show it

#1 stiggy87 closed 11 years ago
1