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cms-L1TK
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project_generation_scripts
Python scripts to generate the wiring map of the tracklet pattern recognition & the top-level HDL that calls the HLS modules in the Hybrid Chain.
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Add FT_bx_out_vld signal to output
#63
mcoshiro
opened
5 days ago
0
FPGA2 Project PR2
#62
aryd
closed
5 days ago
0
Port matching for MPAR inputs to TrackBuilder
#61
aehart
closed
1 month ago
0
first FPGA with merged TPARs
#60
jasonfan393
opened
2 months ago
1
Timing improvements
#59
aehart
closed
1 month ago
0
TrackBuilder fixes
#58
aehart
closed
3 months ago
0
update for new binned memories and first split-fpga chain
#57
jasonfan393
closed
4 months ago
0
TrackBuilder updates
#56
aehart
closed
5 months ago
0
SW/FW synchronization
#55
aehart
closed
5 months ago
0
Updates to remove the generate statements
#54
aryd
closed
7 months ago
5
Combined modules memory delay module and seed stub indices
#53
aryd
closed
10 months ago
1
add pipeline modules needed in full-barrel combined chain
#52
jasonfan393
closed
10 months ago
1
Modifications to allow generated configurations for the combined module chain
#51
aryd
closed
1 year ago
0
move TP LUTs into HLS top function, remove lut modules
#50
jasonfan393
closed
1 year ago
0
update to VMSME memories for Combined module chains
#49
jasonfan393
closed
1 year ago
0
Barrel-only test-bench fix
#48
aehart
closed
1 year ago
1
Removed getDirSCRIPT
#47
aehart
closed
1 year ago
0
Fixes to #45
#46
aehart
closed
1 year ago
0
Updated the scripts to support generation of files for a CM (slim) chain
#45
aryd
closed
1 year ago
2
Barrel config order
#44
aehart
closed
2 years ago
0
Shebang update
#43
meisonlikesicecream
closed
2 years ago
9
Changes for barrel-only config
#42
aehart
closed
2 years ago
4
Update default MemPrints directory and FullMatch memory port names
#41
meisonlikesicecream
closed
2 years ago
0
Fixed HW problems with START signals
#40
tomalin
closed
2 years ago
0
Fix to FIFOs in test-bench
#39
tomalin
closed
2 years ago
2
Fixed bug in HLS parser
#38
tomalin
closed
2 years ago
15
Updated phibinword for IR
#37
meisonlikesicecream
closed
2 years ago
9
Fixed incorrect file directories and names in generated tb
#36
meisonlikesicecream
closed
2 years ago
0
Generate testbench
#35
meisonlikesicecream
closed
2 years ago
0
Fix issue that VHDL variables cant start with number
#34
tomalin
closed
2 years ago
0
Project generation script generate illegal VHDL
#33
pwittich
closed
2 years ago
1
Add support for Python3
#32
pwittich
closed
3 years ago
1
option to disable root (reduce dependencies)
#31
pwittich
closed
3 years ago
4
generator_hdl.py crash in TC.
#30
tomalin
opened
3 years ago
1
update doc to say wiring files now made by C++ and archive old wiring…
#29
tomalin
closed
3 years ago
0
Add nentries ports for allstub and allproj if end of chain
#28
meisonlikesicecream
closed
3 years ago
0
TrackBuilder support
#27
aehart
closed
3 years ago
13
Functions for getting a string version of the enums
#26
meisonlikesicecream
closed
3 years ago
5
Use arrays & generate loops for TE LUT tables
#25
tomalin
opened
3 years ago
0
EOF newlines
#24
aehart
closed
3 years ago
0
IR-VMR Chain
#23
meisonlikesicecream
closed
3 years ago
18
Update memory bit widths
#22
tomalin
closed
3 years ago
0
Delete HourGlassConfig.py and Wires.py after the synchronization
#21
pwittich
closed
3 years ago
1
Fix TE-TC chain
#20
fatimayousuf
closed
3 years ago
10
Use arrays & loops to shorten top-level VHDL
#19
tomalin
closed
3 years ago
0
Added script to create a reduced configuration.
#18
trholmes
closed
3 years ago
28
merge master
#17
fatimayousuf
closed
3 years ago
0
Make compatible with new tf_mem version that uses array for nentries …
#16
tomalin
closed
3 years ago
2
Test regions of modules
#15
fatimayousuf
closed
3 years ago
13
Remove unwanted nEntries ports, update unusedproj.dat, use tf_mem*.vhd & tf_pkg.vhd
#14
tomalin
closed
3 years ago
4
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