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enjoy-digital
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litescope
Small footprint and configurable embedded FPGA logic analyzer
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Trying to run litescope_cli fails with missing attribute 'trigger_enable'
#46
bjonnh
closed
1 year ago
2
software/litescope_cli: pass full path of csv file to driver.
#45
zeldin
closed
1 year ago
2
Don't dump VCD values if unchanged
#44
jevinskie
closed
1 year ago
1
vcd: creates gtkw file if filter_*.txt file is present
#43
fjullien
opened
2 years ago
1
Check subsampling value for overflow.
#42
jevinskie
opened
2 years ago
1
core: Change upload protocol to allow bursting through xBone
#41
smunaut
closed
2 years ago
2
VCD: Add samplerate support to fix displayed timestamps
#40
jevinskie
closed
2 years ago
3
Flag to generate documentation "--doc" is not working
#39
zeeshandildar-rs
closed
2 years ago
1
Fix hex value trigger
#38
troibe
closed
2 years ago
2
allow custom csr.csv location
#37
dayjaby
closed
2 years ago
1
litescope/core: add function to clear scope
#36
DurandA
closed
2 years ago
2
software/dump: add JSON dump
#35
DurandA
closed
2 years ago
1
Dump to JSON instead of .py
#34
DurandA
closed
2 years ago
0
dump.vcd is empty when debugging via PCIe interface
#33
jimmymagemtek
closed
2 years ago
1
Attributes (like trigger_enable) not defined in "LiteScopeAnalyzerDriver" class
#32
jimmymagemtek
closed
3 years ago
9
Fix the cli error messages to make it clearer when you need to provide more CSVs
#31
sthornington
closed
2 years ago
3
litescope/core: add option to register input signals to cut timings
#30
jedrzejboczar
closed
2 years ago
3
a more detailed explanation for some of the litescope_cli arguments
#29
gsomlo
opened
3 years ago
0
Getting empty wave forms
#28
20Mhz
closed
3 years ago
1
Fix: 2 signals in the storage class belong to the wrong clock domain
#27
cklarhorst
closed
3 years ago
1
Question about the Asyncfifo in the storage class
#26
cklarhorst
closed
3 years ago
8
Fix: A WaitTimer belongs to the wrong clock domain (trigger flush)
#25
cklarhorst
closed
3 years ago
1
Feedback / Contribution / Support
#24
enjoy-digital
opened
3 years ago
0
Is it possible to debug the litedram phy with litescope?
#23
cklarhorst
closed
3 years ago
2
Add a script for testing LiteScope
#22
jedrzejboczar
closed
3 years ago
4
Combination of triggers
#21
fjullien
opened
4 years ago
0
Configure maximum clocks between triggers
#20
fjullien
opened
4 years ago
0
Add release
#19
FFY00
closed
4 years ago
1
Display FSM states or any number to text in VCD file
#18
fjullien
opened
4 years ago
0
Add a virtual trigger signal in VCD file to mark trigger point
#17
fjullien
closed
3 years ago
3
software/dump/sigrok: Support width > 1.
#16
zyp
closed
4 years ago
2
Missing csr.csv does not trigger an explicit error in LiteScopeAnalyzerDriver
#15
Acathla-fr
opened
4 years ago
1
Use cpu instead of cpu_or_bridge in examples
#14
DurandA
closed
4 years ago
1
Arty fast scope
#13
keesj
closed
5 years ago
3
analyzer-driver: use default depth from config
#12
xobs
closed
5 years ago
1
add trigger depth option
#11
xobs
closed
5 years ago
1
Add edges
#10
bunnie
closed
5 years ago
5
Fix all remaining indentation issues in python code
#9
felixheld
closed
6 years ago
0
Support pulseview / sigrok directly
#8
mithro
opened
6 years ago
11
Add back support for run length encoding
#7
mithro
opened
6 years ago
1
Allow a trigger pattern (rather than just a single trigger value)
#6
mithro
closed
5 years ago
4
What replaces "LiteScopeLogicAnalyzerDriver" class?
#5
mithro
closed
6 years ago
4
Need a reset signal on litescope?
#4
mithro
closed
7 years ago
2
Allow connection settings after CSV file loading
#3
mithro
closed
7 years ago
1
Adding a .gitignore
#2
mithro
closed
7 years ago
1
Support Record objects.
#1
mithro
closed
7 years ago
1