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riscv-qemu
QEMU with RISC-V (RV64G, RV32G) Emulation Support
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Add RVE register bounds checks to Base ISA ('I'/'E') in translate.c
#144
michaeljclark
opened
6 years ago
0
RISV-V: fix setting timecmp_lo
#143
exokortex
closed
6 years ago
1
sifive_plic mismatch between pending and priority base address
#142
vsiles
closed
6 years ago
3
Populate mtval with instruction bytes on illegal instruction traps
#141
michaeljclark
opened
6 years ago
0
Issue with the CSRRS instruction
#140
vsiles
closed
6 years ago
1
RV64 mstatus/status: SXL and UXL are not correctly implemented
#139
vsiles
opened
6 years ago
2
Why is '-nographic' required to use qemu ?
#138
vsiles
closed
6 years ago
2
qemu-system-riscv32 store doesn't modify the memory during a `sw ra, 12(sp)`
#137
vsiles
opened
6 years ago
18
Allow mstatus.T* bits to be set.
#136
msuozzo
closed
6 years ago
3
linux-user riscv32 stat structure doesn't match glibc/musl
#135
michaeljclark
opened
6 years ago
9
I can't do git clone
#134
yosukezith
closed
6 years ago
1
RISC-V: Implement TSR, TW, and TVM for privileged ISA v1.10.
#133
msuozzo
closed
6 years ago
1
WFI doesn't return when a IPI is issued
#132
atishp04
opened
6 years ago
9
How to skip reset_vec execution before user program?
#131
sergeysmolov
opened
6 years ago
2
hw/riscv: add missed header files inclusion
#130
frantony
closed
6 years ago
3
riscv linux-user should align stack to 16-byte boundary
#129
michaeljclark
opened
6 years ago
1
Possible error in 'jal' insn implementation
#128
sergeysmolov
closed
6 years ago
10
Don't generate exceptions for CSR access in gdbstub.c
#127
michaeljclark
opened
6 years ago
0
Generate illegal instruction traps for s* CSR accesses if misa.S is not set
#126
michaeljclark
opened
6 years ago
0
Priv 1.10 should use *tval instead of *badaddr
#125
msuozzo
opened
6 years ago
2
qemu-options.hx: Add a missing '\n'
#124
twd2
closed
6 years ago
1
Qemu 2.12 fixes
#123
michaeljclark
closed
6 years ago
0
Qemu 2.12 fixes
#122
michaeljclark
closed
6 years ago
0
The continuity of this repo
#121
NonerKao
closed
6 years ago
2
RISC-V: Fix isa string logic bug, use popcount to count bits
#120
michaeljclark
closed
6 years ago
1
Fix riscv isa string
#119
michaeljclark
closed
6 years ago
0
softfloat: fix crash on int conversion of SNaN
#118
michaeljclark
closed
6 years ago
0
softfloat: fix crash on int conversion of SNaN
#117
michaeljclark
closed
6 years ago
0
Qemu upstream v8.2
#116
michaeljclark
closed
6 years ago
0
RISC-V Privileged ISA spec conformance fixes and cleanup
#115
michaeljclark
closed
6 years ago
2
Mask mie/mip fields depending on whether S mode is enabled (misa.S)
#114
michaeljclark
opened
6 years ago
0
Drop writes to satp and return 0 when misa.S is set and no MMU is present.
#113
michaeljclark
closed
6 years ago
2
Trivial fixes to v8
#112
michaeljclark
closed
6 years ago
1
Implement support for IEEE 754-201x minimumNumber/maximumNumber
#111
michaeljclark
closed
6 years ago
1
Support for RTC in virt machine
#110
davidlt
opened
6 years ago
3
riscv: Respect the -initrd flag.
#109
shlevy
closed
6 years ago
15
implement TSR, TW and TVM for privileged ISA v1.10
#108
michaeljclark
opened
6 years ago
7
Fix a bug when sfence.vma is passed (rs2) arguments
#107
heshamelmatary
closed
6 years ago
5
RISC-V - atomic_read breaks RV64 build on i386
#106
michaeljclark
closed
6 years ago
4
RISC-V - Make updates to PTE accessed and dirty bits atomic
#105
michaeljclark
closed
6 years ago
3
RISC-V: Fix CONFIG_USER_ONLY build.
#104
sorear
closed
6 years ago
3
RISC-V: mttcg is incompatible with atomic PTE updates
#103
sorear
closed
6 years ago
32
cleanup and locking improvement for local interrupts
#102
sorear
closed
6 years ago
0
"Register 3921 is not available" when debugging https://github.com/schoeberl/cae-examples on qemu
#101
zakkak
closed
5 years ago
42
riscv-qemu does not compile
#100
ForceFaction
closed
6 years ago
2
Not found bblvmlinuxinitramfs_v1.10
#99
hoangt
closed
6 years ago
7
Hardware Performance Monitor Privileged V1.10 Support
#98
song10
closed
6 years ago
6
QEMU RISCV generates illegal instruction on csrrw
#97
rtcw50
closed
6 years ago
2
Add missing process_queued_cpu_work
#96
andreas-schwab
closed
6 years ago
1
The result of format conversion on an NaN must be a quiet NaN.
#95
darius-bluespec
closed
6 years ago
1
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