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chipsalliance
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VeeRwolf
FuseSoC-based SoC for VeeR EH1 and EL2
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Unsupported board in build Zephyr applications
#21
cst-kirank
opened
3 years ago
6
Running pre-compiled zephyr examples failed
#20
cst-kirank
closed
3 years ago
2
modifed the README for SweRV-EL2zybo
#19
altuSemi
closed
3 years ago
0
Adding a new target, configuring the el2 core
#18
altuSemi
closed
3 years ago
1
SImulation run error
#17
altuSemi
closed
3 years ago
1
VERSION_PATCH macro not defined
#16
luispimo
closed
2 years ago
2
build w/ fusesoc run --target=sim swervolf fails when generating swervolf-intercon:0.7
#15
profroyk
closed
3 years ago
4
Zephyr with adxl362 fails to compile
#14
ddandare
opened
4 years ago
1
Updated OpenOCD .cfg files for proper ICACHE flush
#13
JanMatCodasip
closed
3 years ago
5
Riviera-PRO common compilation
#12
dawidzim
closed
4 years ago
2
Compilation failed for EH1 with Verilator
#11
tunghoang290780
closed
4 years ago
1
Replace deprecated AXI infrastructure
#10
olofk
closed
4 years ago
6
Verilog testbench updated to support newer jtag_vpi:0-r5.
#9
JanMatCodasip
closed
4 years ago
3
Write Buffer coalescing in compliance tests
#8
Podgorny98
closed
2 years ago
3
added missing compilation mode in core
#7
dawidzim
closed
4 years ago
1
support for Riviera-PRO
#6
dawidzim
closed
4 years ago
3
Incompatible modport connection in axi_node_wrap_with_slives
#5
dawidzim
closed
4 years ago
2
Is it OK to simulate under VCS?
#4
zhanjf
closed
4 years ago
13
error during run simulation
#3
zhanjf
closed
4 years ago
1
Synthesis fails on Vivado 2019.1
#2
kammoh
closed
4 years ago
9
Compilation error
#1
tunghoang290780
closed
4 years ago
3
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