jeanthom gram issues - Githubissues

jeanthom / gram

DDR3 controller for nMigen (WIP)

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Import Libre-SOC/Raptor Computing System patches

#55 jeanthom opened 11 months ago
0
Change primitive for Address/Command output

#54 jeanthom opened 4 years ago
1
Multiplexer bug is not detected by test suite

#53 jeanthom opened 4 years ago
0
Move DQS related code into a DQSGroup elaboratable

#52 jeanthom opened 4 years ago
1
DQSBUFM's pause/readclksel sequence is wrong

#51 jeanthom closed 4 years ago
0
Timing violations reported by FakePHY

#50 jeanthom closed 4 years ago
5
Wishbone ack doesn't take rddata_valid into account

#49 jeanthom closed 4 years ago
2
Replace asserts with proper exceptions

#48 jeanthom closed 4 years ago
0
Sync data readout to DQSBUFM's datavalid

#47 jeanthom closed 4 years ago
0
Publish gram on PyPI

#46 jeanthom opened 4 years ago
0
PyPI package name conflict

#45 jeanthom opened 4 years ago
1
sel signal is buggy

#44 jeanthom closed 4 years ago
0
Default to SEL=1 if SEL=0

#43 jeanthom closed 4 years ago
0
Add cti and bte to Wishbone frontend

#42 jeanthom opened 4 years ago
0
Customizable data width on wishbone frontend

#41 jeanthom closed 4 years ago
1
Externalize RoundRobin

#40 jeanthom closed 4 years ago
2
Reliability issues when doing memtests

#39 jeanthom opened 4 years ago
14
Use upstream platform file

#38 jeanthom closed 4 years ago
1
Burst detection is not working

#37 jeanthom closed 4 years ago
2
Read issues after a write transaction

#36 jeanthom closed 4 years ago
1
Write transactions aren't properly detected by the DRAM model

#35 jeanthom closed 4 years ago
2
max_time is never set to 1 when time counter is null (in Icarus Simulation)

#34 jeanthom closed 4 years ago
3
Parallelize unit tests

#33 jeanthom closed 4 years ago
1
Fix bank activation failure

#32 jeanthom closed 4 years ago
2
Fix tDLLK violation

#31 jeanthom closed 4 years ago
1
Report software version in CI

#30 jeanthom closed 4 years ago
3
DRAM is not responding to read requests

#29 jeanthom closed 4 years ago
2
Include CRG in gram

#28 jeanthom closed 4 years ago
0
Use PinsN for RAS/CAS/WE

#27 jeanthom closed 4 years ago
3
Add ECP5 builds to SourceHut builds

#26 jeanthom opened 4 years ago
1
Add SymbiYosys to SourceHut builds

#25 jeanthom closed 4 years ago
2
Long critical path between refresher and somewhere in controller

#24 jeanthom closed 4 years ago
1
ECP5 CRG is wonky

#23 jeanthom closed 4 years ago
0
AXI frontend

#22 jeanthom opened 4 years ago
0
Use Up-Down converters from nmigen-soc

#21 jeanthom closed 4 years ago
0
Add more assertions to the CRG simulation

#20 jeanthom closed 4 years ago
1
Use dramsync as the default clock domain everywhere in gram

#19 jeanthom closed 4 years ago
0
ECP5 PHY signal lignes are invalid

#18 jeanthom closed 4 years ago
2
PHY unit testing

#17 jeanthom closed 4 years ago
1
Don't instantiate arbiters if there is only one master in crossbar

#16 jeanthom closed 4 years ago
1
Generate MRx values according to DRAM chip specs

#15 jeanthom opened 4 years ago
1
"a" signal in RefreshExecuter and RefreshSequencer is too small

#14 jeanthom closed 4 years ago
0
Critical path too long in dram core

#13 jeanthom closed 4 years ago
5
Avoid usage of getattr

#12 jeanthom closed 4 years ago
1
DQS group mismatch

#11 jeanthom closed 4 years ago
5
DQSBUFM not connected to top level

#10 jeanthom closed 4 years ago
1
ECP5DDRPHY is filled with "Case" statements but nMigen doesn't see anything wrong with it

#9 jeanthom closed 4 years ago
0
Memtest fail

#8 jeanthom closed 4 years ago
12
Bring back testing in gram

#7 jeanthom opened 4 years ago
5
Wishbone DRAM content interface debugging

#6 jeanthom closed 4 years ago
2