oddball ipxact2systemverilog issues

oddball / ipxact2systemverilog

Translates IPXACT XML to synthesizable VHDL or SystemVerilog

GNU General Public License v2.0

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issues

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Vermaete/sphinx

#53 vermaete closed 1 year ago
0
Vermaete/readonly

#52 vermaete closed 1 year ago
0
Vermaete/empty field descriptions

#51 vermaete closed 1 year ago
1
Similar enums are not generated

#50 brucebenedictus closed 1 year ago
1
Fill all the unused holes in a register.

#49 brucebenedictus closed 1 year ago
2
Fill all the unused holes in a register.

#48 brucebenedictus closed 1 year ago
1
vhdl: std_ulogic (default) or std_logic

#47 vermaete closed 1 year ago
0
vhdl: fixed issue when the value of the enums is in hex.

#46 vermaete closed 1 year ago
1
Fix the condition to check if there is a description on addressBlock.

#45 vermaete closed 1 year ago
0
A few changes

#44 vermaete closed 1 year ago
1
ipxact2hdlCommon.py returnRstTitle returns hardcoded string iso addressBlock.name

#43 wolfgang-blaszczyk closed 1 year ago
5
ipxact2rst can not handle xml with 
 characters for linefeed

#42 wolfgang-blaszczyk closed 1 year ago
2
Fix when having no or empty description for register fields

#41 vermaete closed 1 year ago
0
ci/cd: drop python2 and move python3 to 3.11

#40 vermaete closed 1 year ago
0
fix for the 'PublicConvFunct' config option

#39 vermaete closed 1 year ago
3
change README from ReStructuredText to MarkDown

#38 oddball closed 1 year ago
0
adding #ip-xact

#37 vermaete closed 2 years ago
1
Expose record-to-sulv and sulv-to-record functions in the vhdl generated package

#36 brucebenedictus closed 2 years ago
2
Created class to generate C header file from IPXACT

#35 EdwinElshoud closed 2 years ago
5
grr

#34 oddball closed 3 years ago
0
test build of PR

#33 josefinebofeldt closed 3 years ago
0
Added a VHDL function to reset a specific register. Nbr 2

#32 oddball closed 3 years ago
0
Added a VHDL function to reset a specific register.

#31 oddball closed 3 years ago
0
Add pointers to additional schemas

#30 joseph1996sh opened 3 years ago
2
Added a VHDL function to reset a specific register.

#29 vermaete closed 3 years ago
4
Verilator support

#28 oddball closed 3 years ago
0
Systemverilog code does not compile

#27 g-lesssard closed 3 years ago
8
fix the reversed register field descriptions

#26 vermaete closed 3 years ago
0
Register description is not mandatory

#25 vermaete closed 3 years ago
1
Some work on the enumerations.

#24 vermaete closed 3 years ago
0
Removed some debug remaining.

#23 vermaete closed 3 years ago
3
Add test of that the systemverilog code can be compiled with slang

#22 oddball closed 3 years ago
2
Vermaete

#21 oddball closed 3 years ago
0
trigger ci

#20 oddball closed 3 years ago
0
trigger circleci

#19 oddball closed 3 years ago
0
Recommended xml schema editor

#18 mm4dd closed 3 years ago
1
some small and none functional changes

#17 vermaete closed 3 years ago
2
Some register and field naming was not correct.

#16 vermaete closed 5 years ago
0
generate c code

#15 oddball closed 2 years ago
3
bad interpreter

#14 snarum-NIS closed 6 years ago
3
Validation Failed - user left in the dark ... :)

#13 galaviel closed 6 years ago
2
1.0.2

#12 oddball closed 7 years ago
0
Added circle.yml file

#11 oddball closed 7 years ago
0
Question about the xml parser

#10 stzer closed 6 years ago
2
Prepare pip

#9 oddball closed 7 years ago
0
Updated URL and fix of vlog compile error

#8 maxbjurling closed 8 years ago
1
some smaller stuff

#7 vermaete closed 8 years ago
0
Fix so there can be space between two register fields

#6 vermaete closed 10 years ago
3
The end character of a RestructuredText table raw was wrong ('+') i.s.o....

#5 vermaete closed 10 years ago
1
added a note about a way to get the XML schema local

#4 vermaete closed 10 years ago
2