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openhwgroup
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cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
https://docs.openhwgroup.org/projects/cva6-user-manual/
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Add lambda function to sort lint summary according to severity
#2316
Asmaa-Kassimi
opened
1 minute ago
0
Add RISCV documentation for cv64a6_mmu
#2315
LQUA
opened
5 minutes ago
0
feat: update cva6_hpdcache_icache_if_adapter (support continuous virtual address requests)
#2314
takeshiho0531
opened
6 minutes ago
0
Fix benchmark.sh with correct GCC options and order (Fix #2250)
#2313
Gchauvon
opened
11 minutes ago
0
refac: cva6 icache fsm hit
#2312
takeshiho0531
opened
4 hours ago
2
refac: cva6 icache fsm hit
#2311
takeshiho0531
closed
4 hours ago
0
condition csr_regfile.sv
#2310
Asmaa-Kassimi
opened
16 hours ago
1
add UVM interrupt agent
#2309
AyoubJalali
opened
18 hours ago
2
Genesys 2 UART port disables on connect
#2308
benlarsendk
opened
18 hours ago
0
Add illegal instruction to cover corner case in decoder
#2307
AyoubJalali
closed
17 hours ago
1
fix lint errors in csr_regfile.sv
#2306
Asmaa-Kassimi
closed
19 hours ago
1
Bump verif/core-v-verif from `0e97e74` to `4531071`
#2305
dependabot[bot]
closed
1 day ago
1
[Spike Yaml] Integrate Spike Yaml support.
#2304
zchamski
opened
2 days ago
1
superscalar add second ALU
#2303
cathales
closed
2 days ago
1
Bump CVV to fix issue 2484
#2302
AyoubJalali
closed
17 hours ago
2
Bump CVV to use improved scoreboard reporting in tandem simulations.
#2301
zchamski
closed
4 days ago
1
Fix typo on Bitmanip comment
#2300
Gchauvon
closed
4 days ago
0
update expected area
#2299
cathales
closed
4 days ago
1
[BUG] Linking error: undefined reference to htif_t::load_payload
#2298
shreyas-kalikar
opened
5 days ago
3
[BUG] `minstret` and `mcycle` do not increment in debug mode, while `dcsr.stopcount` is set to 0 (normal mode)
#2297
xiaoweish
opened
5 days ago
5
CI: Fix riscv-isa-sim builds
#2296
MarioOpenHWGroup
closed
6 days ago
0
Update uvml_mem use for core-v-verif's PR: 2480/2481/2482
#2295
xiaoweish
closed
6 days ago
3
Add vcs -full64 compile option back
#2294
xiaoweish
closed
6 days ago
1
Add debug_req UVM agent to UVM TB
#2293
xiaoweish
opened
1 week ago
7
Errors on synthesizing and programming CVA6 on Genesys II
#2292
benlarsendk
closed
18 hours ago
1
Bump core/cache_subsystem/hpdcache from `25ffa34` to `27f069b`
#2291
dependabot[bot]
opened
1 week ago
1
Error while running riscv-arch-test
#2290
abhikutari
opened
1 week ago
1
[BUG] stall_instr_fetch signal in core/id_stage.sv will not be driven if CVA6Cfg.RVZCMP is disabled
#2289
ckf104
opened
1 week ago
0
Draft extended hpdcache
#2288
takeshiho0531
opened
1 week ago
13
Makefile : passing the tandem_enable value into UVM testbench
#2287
AyoubJalali
closed
6 days ago
1
[gen_from_riscv_config] add custom-gen.yaml support / fix hyperlinks in csr...
#2286
AbdessamiiOukalrazqou
closed
1 week ago
0
Fix mstatus.mpp in relation to the possible legal values
#2285
JeanRochCoulon
closed
1 week ago
4
Fix WARL behavior of MPP in MSTATUS
#2284
Moschn
closed
1 week ago
0
Fix WARL behavior of MPP
#2283
Moschn
closed
1 week ago
1
decoder.sv: add checks for some B instructions (fix #2276)
#2282
ASintzoff
closed
1 week ago
1
fix lint errors in csr_regfile.sv
#2281
Asmaa-Kassimi
closed
1 week ago
9
[BUG] B extension: incorrect decoding for some instructions in RV32
#2280
ASintzoff
opened
1 week ago
2
Increase max num PMPs to 64
#2279
Moschn
opened
1 week ago
18
superscalar: allow speculative instructions
#2278
cathales
closed
1 week ago
1
[TASK] Implement CVXIF 1.0.0 instruction dedicated to verification
#2277
Gchauvon
opened
1 week ago
0
[BUG] : Decoder Bitmanip instructions
#2276
AyoubJalali
closed
1 week ago
0
Fix the 65x CSR document
#2275
JeanRochCoulon
opened
1 week ago
2
[BUG] : MSTATUS.mpp
#2274
AyoubJalali
closed
1 week ago
7
Use correct fault type for VLSU overflow
#2273
michael-platzer
closed
1 week ago
1
[BUG] LSU overflow (unused vaddr bits unequal) triggers ld/st access fault instead of page fault
#2272
michael-platzer
closed
1 week ago
1
doc: clarify mtval register description when not enabled
#2271
ASintzoff
closed
1 week ago
0
[riscv-config] Update riscv-config tool, CV32A65X specs and the rendering of CSRs.
#2270
zchamski
closed
1 week ago
0
Feat: add add cva6_hpdcache_icache_if_adapter (supports the simplified icache kill mechanism)
#2269
takeshiho0531
closed
1 week ago
6
[BUG] Design doc generation: custom CSRs are missing in the CV32A65X documentation
#2268
zchamski
closed
1 day ago
2
Implement simple uart-based updater for the bootrom
#2267
grg-haas
closed
1 week ago
3
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