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veripool
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verilog-mode
Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.
http://veripool.org/verilog-mode
GNU General Public License v3.0
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Fix verilog-pretty-expr on declarations and update related tests
#1780
gmlarumbe
closed
1 year ago
3
Add variable to adjust aligned comment distance in declarations.
#1779
gmlarumbe
closed
2 years ago
0
Add indentation ignore of multiline defines and custom regexps
#1778
gmlarumbe
closed
2 years ago
0
'verilog-mark-defun' does not mark functions
#1777
gmlarumbe
closed
1 year ago
2
Add a semicolon after module declaration on tests to fix indentation.
#1776
gmlarumbe
closed
2 years ago
0
Add support to align comments in declarations
#1775
gmlarumbe
closed
2 years ago
3
Customize indentation for multi-line parameter lines
#1774
bjourne
closed
1 year ago
7
Wrong alignment of custom type ports
#1773
gmlarumbe
closed
2 years ago
1
verilog-mode-map rebinds delete and backspace keys
#1772
bjourne
opened
2 years ago
3
Fix alignment of first port declaration
#1771
gmlarumbe
closed
2 years ago
1
Fix alignment of declaration of interfaces with modports
#1770
gmlarumbe
closed
2 years ago
0
Fix indentation of classes inside packages
#1769
gmlarumbe
closed
2 years ago
5
Fix indentation after interface class (bug #1047)
#1768
gmlarumbe
closed
2 years ago
0
Fix indentation if verilog-indent-lists is nil
#1767
gmlarumbe
closed
2 years ago
3
Fix issue #1321: incorrect indentation of coverpoints
#1766
gmlarumbe
closed
2 years ago
1
Fix bug in forward-sexp and backward-sexp for some constructs
#1765
gmlarumbe
closed
2 years ago
3
How to disable // Templated comment when using AUTO_TEMPLATE
#1764
kachungwong
closed
2 years ago
2
AUTOINSTPARAM not printing parameters for all modules
#1763
juanyo810
closed
2 years ago
2
AUTO using an ifdef that chooses between two module instances.
#1762
knofr
closed
2 years ago
3
Computing AUTOs with ifdef'd parameter list fails.
#1761
sjalloq
closed
2 years ago
2
Space added in "output" with auto-lineup declarations
#1760
sjalloq
closed
1 year ago
4
Symbol's value as variable is void
#1759
futurehome
closed
2 years ago
2
Is there a variable to control in which column a port name appears?
#1758
cswfb
opened
2 years ago
4
Feature request: multiple regexp patterns be indexed in instance name for AUTO_TEMPLATE
#1757
thfirst
closed
2 years ago
2
How to use defined "parameter FOR_NUMS = 8;" in @for loop
#1756
thfirst
closed
2 years ago
3
fix: should able to declare the input as wire
#1755
kopinions
closed
1 year ago
4
AUTOINPUT can not create signal with nettype
#1754
kopinions
opened
2 years ago
1
Incorrect highlighting of words after "module" or "interface" in a comment
#1753
fnJeff
closed
1 year ago
8
Fontifying of variable names in declarations not working correctly
#1752
fnJeff
opened
2 years ago
6
AUTOINST extra space for "// Templated" on last port of instance
#1751
fnJeff
closed
2 years ago
2
Improving the AUTOINST handling of signed ports
#1750
fnJeff
opened
2 years ago
1
Fix indentation on double curly brackets
#1749
punzik
closed
2 years ago
1
Casting a signal that is an output of an AUTOINST instance output seems to prevent AUTOLOGIC from creating declaration
#1748
fnJeff
closed
2 years ago
2
the support to parameter integer array
#1747
shawn110285
closed
2 years ago
1
Does verilator support the parameter integer array?
#1746
shawn110285
closed
2 years ago
1
it's possible to keep the order of input and output port when auto inst?
#1745
zhanjf
closed
2 years ago
1
Fix indentation on double curly brackets (issue #1719)
#1744
punzik
closed
2 years ago
0
Fix indentation within generate construct after always (#1404,#1257)
#1743
punzik
closed
2 years ago
3
Fix indentation (issue #1404, #1257 and #1719)
#1742
punzik
closed
2 years ago
1
verilog-auto-inst-sort does not work
#1741
zhanjf
closed
2 years ago
8
"System verilog attribute on pin" autoinsted by AUTO_TEMPLATE
#1740
13771915047
closed
2 years ago
2
AUTO_TEMPLATE that applies only to a specific instance
#1739
imgod2u
closed
2 years ago
1
Verilog-A `analog` block support
#1738
danmcmahill
closed
2 years ago
2
Make '_' a symbol character
#1737
smithzvk
closed
2 years ago
5
`end // UNMATCHED !!` after `analog begin` in Verilog-A
#1736
danmcmahill
closed
2 years ago
3
Prompt: File TIE.v is large (27.9M), really open? (y or n)
#1735
imgod2u
closed
2 years ago
1
Can a lisp expression in an AUTO block use a parameter from a package?
#1734
sjalloq
closed
2 years ago
8
Ports are always sorted even verilog-auto-inst-sort is set to nil
#1733
kevinyuan
closed
2 years ago
1
/*AUTOWIRE*/ is ignoring existing declaring of typedef objectss
#1731
afuller525
closed
2 years ago
2
Get the capital case of the @ variable
#1730
imgod2u
closed
3 years ago
1
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