issues
search
veripool
/
verilog-mode
Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.
http://veripool.org/verilog-mode
GNU General Public License v3.0
247
stars
90
forks
source link
issues
Newest
Newest
Most commented
Recently updated
Oldest
Least commented
Least recently updated
Module name not highlighted unless followed by '(' on the same line
#1679
vinamarora8
closed
4 years ago
2
Adds syntax highlighting for identifiers in declaration statements
#1678
vinamarora8
closed
4 years ago
2
Feature request: Variable name syntax highlighting
#1677
vinamarora8
closed
4 years ago
2
Current Mode of Disabling of AUTOs when expansion fails
#1676
engrvns
closed
4 years ago
1
Using regex/glob for module/instance in AUTO_TEMPLATE
#1675
engrvns
closed
4 years ago
1
Any Debug Messages to localize and aid faster debug of Unbalanced parentheses inside verilog AUTOs
#1674
engrvns
closed
4 years ago
1
Use of Ordered AUTO_TEMPLATEs to simplify code integration
#1673
engrvns
opened
4 years ago
3
AUTOWIRE declares array of typedef as signal
#1672
imgod2u
closed
4 years ago
1
AUTOOUTPUT signal size takes genvar variable instead of signal size from definition
#1671
Haim68
closed
4 years ago
1
Auto declaration of undeclared signals that can not be generated by AUTOWIRE and AUTOREG
#1670
guoqinglei
closed
4 years ago
1
How to write a AUTO rule for creating AUTOOUTPUTS of internal signals
#1669
engrvns
closed
4 years ago
4
AUTOASSIGNMODPORT and AUTOASSIGNMODPORT direction
#1668
marmarjohnson
opened
4 years ago
1
Replacing instance port parameters with it's values in parent module ports - An issue with usage of verilog-auto-inst-param-value
#1667
engrvns
opened
4 years ago
1
verilogmode re-indenting certain keywords
#1666
rasmus-madsen
closed
4 years ago
10
connectmodule/endconnectmodule support
#1665
danmcmahill
closed
4 years ago
3
Order of ports in instance -> how to reorder?
#1664
ldm1417
closed
3 years ago
5
Question: AUTOINSTPARAM use with dependent parameters
#1663
veripoolbot
closed
4 years ago
7
How to access multiple capture groups in AUTOINST REGEXP?
#1662
veripoolbot
closed
4 years ago
3
Question: Module port list using AUTOARG cant pass an Interface
#1646
veripoolbot
closed
4 years ago
3
Fix typo "italis" -> "italic"
#20
cmarqu
closed
4 years ago
1
Indenting after string parameter results in error with verilog-indent-lists nil
#1645
veripoolbot
closed
4 years ago
4
Question: protected .svp files in batch mode
#1528
veripoolbot
closed
4 years ago
1
Skip over base-64-encoded protected data while reading declarations
#19
berendo
closed
4 years ago
3
Handle line directives in port list while "parsing" AUTOINSTed modules
#18
berendo
closed
4 years ago
4
Emacs batch mode autos fails with .va files
#1527
veripoolbot
closed
4 years ago
3
SystemVerilog cast on input ports causes signal to be ignored
#1526
veripoolbot
closed
3 years ago
28
Wrong indentation after SV streaming statement
#1516
veripoolbot
closed
3 years ago
1
Question: not expose specific block parameter to the higher hierarchy level or expose it with its default value
#1499
veripoolbot
closed
4 years ago
1
replacing parameter with actual values
#1498
veripoolbot
closed
4 years ago
3
Wrong statement continue alignment.
#1495
veripoolbot
opened
4 years ago
4
verilog-goto-defun can't not list tasks and functions
#1492
veripoolbot
closed
4 years ago
1
Question: Auto-indent inside macros systemverilog
#1486
veripoolbot
closed
4 years ago
4
struct typedef io decleration with packed array does not instantiated correctly with AUTOINST
#1485
veripoolbot
closed
4 years ago
1
how to import function
#1480
veripoolbot
closed
4 years ago
1
Question: Preferred method for dealing with vendor-library primitives
#1472
veripoolbot
closed
5 years ago
2
Describe how to find source file to debug autos
#1471
veripoolbot
closed
5 years ago
3
Documentation bugs
#1466
veripoolbot
closed
5 years ago
2
AUTOINST adds outputs that aren't in module
#1464
veripoolbot
closed
5 years ago
2
Structs as output ports don't work with stub generation recipe
#1461
veripoolbot
closed
5 years ago
2
endclocking not indented properly on default clocking blocks
#1457
veripoolbot
closed
5 years ago
3
Question: Recursively reading files from verilog-library-flags
#1454
veripoolbot
closed
5 years ago
3
AUTOLOGIC/AUTOINST for unpacked array signal input to submodule
#1453
veripoolbot
opened
5 years ago
3
Use AUTO_TEMPLATE number from instance name to control string in port signalname
#1452
veripoolbot
closed
5 years ago
1
AUTOINOUTMODULE not working in emacs batch mode
#1450
veripoolbot
closed
5 years ago
6
AUTOs fails with embedded ifndef in parameters
#1448
veripoolbot
closed
5 years ago
4
Expand AUTOINST default values for parameters
#1447
veripoolbot
opened
5 years ago
4
SystemVerilog interface indentation in module declaration
#1446
veripoolbot
opened
5 years ago
2
Question: How can I use AUTOs to add the input/output attribution info. like "i_/o_" or "_i/_o" to the wires?
#1417
veripoolbot
closed
5 years ago
3
problems getting Verilog-batch-auto to work with library file
#1416
veripoolbot
closed
5 years ago
5
Question: Usage of '*' in verilog-library-directories
#1411
veripoolbot
closed
5 years ago
1
Previous
Next